Generally, when two circuits having different sizes of signal voltages are connected to each other, a level shift circuit is positioned between the circuits and changes the sizes of signal voltages. Such a level shift circuit is mainly used when the sizes of signal voltages are changed from a smaller voltage range to a larger voltage range.
In particular, in a circuit for driving a flat display device, such as a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED) or an electro-luminescent display (ELD), a digital circuit portion is designed to operate with a low voltage for low power consumption, and due to the characteristic of a panel for driving a element, such as a liquid crystal (LC) or organic light emitting diode (OLED), a level shift circuit is used to convert a signal in the digital circuit portion to be appropriate to the range of a voltage for driving the panel.
An example of a conventional capacitive coupling type level shift circuit is illustrated in FIG. 1 (S. C. Tan, et al., Low Power CMOS Level Shifters by Bootstrapping Technique, Electronics letters, August 2002, Vol. 38, No. 16).
As illustrated in FIG. 1, in the level shift circuit, two N-type transistors N4 and N5 and two diode-coupled N-type transistors N2 and N3, and two capacitors C1 and C2 are connected to an input port, and a P-type transistor P1 and an N-type transistor N1 are connected to an output port.
In the level shift circuit using capacitive coupling having the above structure, as an input signal IN shown in (a) of FIG. 2 and an inverted input signal INb shown in (b) of FIG. 2 are input to the input port, a voltage at a node A is as shown in (c) of FIG. 2 by the capacitor C1 and the diode-coupled N-type transistor N2, and a voltage at a node B is as shown in (d) of FIG. 2 by the capacitor C2 and the diode-coupled N-type transistor N3. An output voltage signal OUT at the output port is level shifted, as shown in (e) of FIG. 2, according to voltage signals at the nodes A and B and a voltage signal of the inverted input signal INb. That is, the input signal IN having an operating range of GND˜VDDH is level shifted into the output signal OUT having an operating range of VSS˜VDDH.
The level shift circuit using capacitive coupling has low power consumption. On the other hand, since two capacitors which take a larger area than the area of a transistor are used, the left shift circuit has a large size. In addition, a feedback operation is performed so as to disturb a normal operation at the nodes A and B that are capacitive-coupled when the input signal IN is transited, and there is the possibility of the occurrence of an unstable operation. Thus, the conventional level shift circuit is not suitable for use in a circuit for driving a flat display.
As another example of a conventional level shift circuit, a latch-type level shift circuit generally used in a circuit for driving a flat display is shown in FIG. 3. As illustrated in FIG. 3, the level shift circuit includes two P-type transistors P3 and P4 and two N-type transistors N6 and N7.
An input signal IN is input to a gate of the P-type transistor P3, an inverted input signal INb is input to a gate of the P-type transistor P4, and drains of the P-type transistors P3 and P4 are connected to a positive first source voltage VDDH. A drain of the N-type transistor N6 is connected to a source of the P-type transistor P3, a gate of the N-type transistor N6 is connected to a drain of the P-type transistor P4, a drain of the N-type transistor N7 is connected to the source of the P-type transistor P4, a gate of the N-type transistor N7 is connected to the source of the P-type transistor P3, and sources of the N-type transistors N6 and N7 are connected to a negative second source voltage VSS. The level shift circuit constructed in this way and shown in FIG. 3 has a cross-coupled latch structure.
In the level shift circuit having the cross-coupled latch structure, as an input signal IN shown in (a) of FIG. 4 and an inverted input signal INb shown in (b) of FIG. 4 are input to gates of the P-type transistors P3 and P4, respectively, an output signal OUT at an output port is level shifted, as shown in (c) of FIG. 4, and an inverted output signal OUTb which is inverted from the output signal OUT, is formed at a connection node between the P-type transistor P3 and the N-type transistor N6, that is, a gate terminal of the N-type transistor N7, as shown in (d) of FIG. 4. That is, the input signal IN having an operating range of GND˜VDDH is level shifted into the output signal OUT having an operating range of VSS˜VDDH.
The operation of the level shift circuit having the cross-coupled latch structure will now be described in detail. In other words, when the input signal IN is changed from a ground voltage GND to the positive first source voltage VDDH, the P-type transistor P3 is turned off. At this time, the P-type transistor P4 driven by the inverted input signal INb is turned on and starts charging the output port to the positive first source voltage VDDH. However, in the state where the P-type transistor P4 is turned off and the output port is not sufficiently charged to the positive first source voltage VDDH, the N-type transistor N6 is weakly turned on. As such, it takes time to charge the inverted output signal node from the positive first source voltage VDDH to the negative second source voltage VSS. Accordingly, the N-type transistor N7 is not turned off by the inverted output signal OUTb so that a time period in which the P-type transistor P4 is turned on by the inverted input signal INb and simultaneously, the N-type transistor N7 is turned on by the inverted output signal OUTb is generated, a pass through current from the positive first source voltage VDDH to the negative second source voltage VSS is generated and power consumption increases accordingly.
Similarly, when the input signal IN is changed from the first source voltage VDDH into the ground voltage GND, the P-type transistor P4 connected to the inverted input port is turned off and the P-type transistor P3 is turned on so that the inverted output signal node is charged to the positive first source voltage VDDH. In this case, the N-type transistor N7 is weakly turned on by the inverted output signal OUTb and the first source voltage VDDH at the output port is not rapidly reduced to the voltage VSS. As a result, the N-type transistor N6 is turned on and generates a pass through current from VDDH to VSS together with the P-type transistor P3 turned on by the input signal IN, and power consumption increases accordingly.
In particular, the above-mentioned problem about large power consumption is associated with a structural disadvantage that, due to the characteristic of a latch structure, speed at which a change of the input signal IN and the inverted input signal INb affects the output signal OUT and the inverted output signal OUTb is very slow, and there is a serious problem about an operating speed, together with the problem about power consumption.
In addition, the number of elements of a main body of a level shift circuit having a latch structure is very small (only 4) on the assumption that the generated inverted input signal INb is used. However, in case of the transistors P3 and P4 connected to the input signal IN and the inverted input signal INb, respectively, the input signal IN and the inverted input signal INb are transmitted to the output port in such a way that voltages of the input signal IN and the inverted input signal INb are changed into currents due to a transconductance characteristic. Thus, the sizes of the transistors P3 and P4 are increased so as to improve a transmission capability and thus, the advantage of area that only four transistors are used may be ambiguous.
In other words, the level shift circuit having the cross-coupled latch structure has very excellent operating stability and thus operates regardless of an initial voltage at each node. However, the level shift circuit has a disadvantage that the amount of a pass through current caused by a short circuit current generated as the N-type transistor and the P-type transistor are simultaneously turned on is large, an operating speed is slow and power consumption is large. Furthermore, the sizes of the transistors P3 and P4 should be increased so as to improve characteristics, and thus the level shift circuit has a disadvantage that the advantage of small size may be ambiguous.